Forum Discussion
KhaiChein_Y_Intel
Regular Contributor
5 years agoHi Gabriele,
Can you create a separate topic and provide the design in the new topic?
In Michael's design, I have tested that the error is fixed by adding the sdc constraint derive_pll_clocks -create_base_clocks
For your design, there might be other root cause and require further investigation.
Thanks.
Best regards,
KhaiY