"Tcl error: ERROR: Argument <node_object> is an object filter that matches no objects. Specify one matches only one object." when using LVDS SERDES IP.

Hi,

May I request the design for investigation?

Thanks.

Hi,

Let me apologize for the late reply.

To share the design with you, I have been trying to reproduce this error in a minimal way. Then I somehow fixed the error.

The reason of this problem is caused by an auto-reset logic attached to the SERDES module. The auto-reset logic was implemented in a wrong way, which does not auto-reset the SERDES. I fixed this logic and the project is compiled successfully.

Thank you,

Yoshitaka

Hi Yoshitaka,

It is glad to hear that you found the root cause. Thanks for the reply. I believe your reply is beneficial to other users.

Thanks.

Best regards,

KhaiY

Hello KhaiY,

we get the same error as described here. We also tried it without the auto-reset port but still we get the same error message. We get the error using version 19.3_pro and 19.4_pro.

The next step was generating an example design using the button within qsys. Creating a quartus project which uses the ed_synth_tx_rx.qsys as top level, we get an similar error. It says "Tcl error: ERROR: Argument <clk_object> is a collection with more than one object. Specify a collection with one object."

The error occurs in line 402 within sdc_util.tcl which is part of altera_lvds_core20. In contrast, the error occurs in line 400 for our design.

Interestingly, creating the same example within quartus 18.0.1, we don't get any error during the timing analyzer step.

Do you have any idea what the problem could be?

Thanks

Michael

Hi Michael,

Can you provide the design.qar for Pro19.4 for investigation?

Thanks.

Best regards,

KhaiY

Hello KhaiY,

I cannot find such a file within the project folder. I found some files in the Altera installation folder. However, I don't think they are relevant.

Can you explain how to find or generate this file?

Thanks

Michael

Hi Michael,

You may generate the .qar file by clicking on Project > Archive Project

Thanks.

Best regards,

KhaiY

Hi KhaiY,

please find attached the qar file of the example design.

Thanks

Michael

Hi Michael,

I have filed a case to our developer. I will update once I received the feedback from the team.

Thanks.

Best regards,

KhaiY

Hi to all,

I have the exact issue (Tcl error: ERROR: Argument <node_object> is an object filter that matches no objects. Specify one matches only one object.) with a design that contains the LVDS SERDES core, in non-DPA mode, during the Timing analyzer phase, running Quartus 19.4.0 Build 64.

The same design works flawlessly in Quartus Pro 19.1.0 Build 240

I tried to clean the project and regenerate the IP cores, but without success. I'm not using Qsys, but the raw IP connected to custom logic. The PLL of LVDS is not external but internal to the SERDES IP.