Forum Discussion
Hello KhaiY,
we get the same error as described here. We also tried it without the auto-reset port but still we get the same error message. We get the error using version 19.3_pro and 19.4_pro.
The next step was generating an example design using the button within qsys. Creating a quartus project which uses the ed_synth_tx_rx.qsys as top level, we get an similar error. It says "Tcl error: ERROR: Argument <clk_object> is a collection with more than one object. Specify a collection with one object."
The error occurs in line 402 within sdc_util.tcl which is part of altera_lvds_core20. In contrast, the error occurs in line 400 for our design.
Interestingly, creating the same example within quartus 18.0.1, we don't get any error during the timing analyzer step.
Do you have any idea what the problem could be?
Thanks
Michael