Forum Discussion
KhaiChein_Y_Intel
Regular Contributor
5 years agoHi,
I received the feedback. You may add the below constraint in the sdc file:
derive_pll_clocks -create_base_clocks
or
In the attached design, you can use the SDC generated for the example design, which already contains this SDC function call:
set_global_assignment -name SDC_FILE lvds_0_example_design/lvds_0_example_design_example_design/ed_synth.sdc
Thanks.
Best regards,
KhaiY