Sytem Verilog one-hot selection

I received a reply from "MySupport" claiming that "unique" is not supported and it is ignored. This can't be 100% true because you get additional warnings when using the keyword with overlapping case items, and the warnings do reference the System Verilog "unique" feature.

I guess the conclusion is that it is supported by the earlier analysis, parsing phases, but it is ignored at actual shyntesis.

I also checked the ModelSim 6.3 release notes and both "unique" and "priority" are now supported. I hope Altera will update their ModelSim version with newer QII releases (and of course, add full support for the keywords in Quartus as well).

MySupport gave you the wrong info. If you look at Quartus II Support for SystemVerilog 2005 in online Help in Quartus II 7.2:

IEEE Subsection Construct Description

10.4 Selection statement Supported (unique/priority supported only on case statements)

I compiled my previous example (without the o = d) in Modelsim 6.3c SE. If sel == 2'b00, then I see the following warning:

# ** Warning: (vsim-8315) unique1.v(5): No condition is true in the unique/priority if/case statement.

As expected, o holds its previous value.

Hi HDL Guru,

I know the online help (and the full manual as well) claims they are supported. I mentioned this already at one of my first posts. But how do you know MySupport is wrong, and not the manual and online help are the ones that are wrong?

I made a couple of tests and it seems indeed the manual is wrong. Not even the parallel semantics seems to be supported (I initially thought the problem was only the full semantics). All you get is some additional warnings at compile time (but not at simulation run-time).

Thanks for testing under ModelSim 6.3. So I was wrong about that. I still think it's not the right simulation behavior. The simulator knows there are no latches, so I don't understand why it preservers the previous value.

I guess I trust the documentation that ships with the tool rather than a support hotline. :)

Hey, you're right! I played around with some nasty non-parallel case statements. Quartus II 7.2 doesn't force parallel implementation. It just gives you a warning about having overlap in a unique case statement. From the looks of things, Quartus II is implementing unique/priority more as an assert about a design property than a direction to implement the logic in a particular way. That's not terribly useful.

I think I'm coming around to your way of seeing things. Personally, I would have preferred that SystemVerilog introduced an equivalent full keyword rather than making unique/priority absorb the semantics. Then I started thinking, these keywords are really just intended to give designers the same semantics as parallel_case, full_case but with some modicum of simulation support. A warning in simulation is better than nothing, as you said.

Finally, Quartus version 8.0 fully supports the SV "unique" keyword in case statements. At least for synthesis, didn't check the Quartus simulator.

Seems to be one of the many new SV features in 8.0, and it is not mentioned in the "what's new" doc. Another very useful new SV feature (undocumented as new) is support for implicit port connections.

I wish Altera would make a comprehensive list of new features in 8.0