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Altera_Forum
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18 years ago

Sytem Verilog one-hot selection

Aren't the new System Verilog case specifiers (unique/priority) supposed to avoid the need of using the synthesis attribute "full_case" ? No matter what I do, I cannot get a one-hot optimized s...
Altera_Forum's avatar
Altera_Forum
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18 years ago

MySupport gave you the wrong info. If you look at Quartus II Support for SystemVerilog 2005 in online Help in Quartus II 7.2:

IEEE Subsection Construct Description

10.4 Selection statement Supported (unique/priority supported only on case statements)

I compiled my previous example (without the o = d) in Modelsim 6.3c SE. If sel == 2'b00, then I see the following warning:

# ** Warning: (vsim-8315) unique1.v(5): No condition is true in the unique/priority if/case statement.

As expected, o holds its previous value.