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Altera_Forum
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18 years ago

Sytem Verilog one-hot selection

Aren't the new System Verilog case specifiers (unique/priority) supposed to avoid the need of using the synthesis attribute "full_case" ? No matter what I do, I cannot get a one-hot optimized s...
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Altera_Forum
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17 years ago

Finally, Quartus version 8.0 fully supports the SV "unique" keyword in case statements. At least for synthesis, didn't check the Quartus simulator.

Seems to be one of the many new SV features in 8.0, and it is not mentioned in the "what's new" doc. Another very useful new SV feature (undocumented as new) is support for implicit port connections.

I wish Altera would make a comprehensive list of new features in 8.0