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Altera_Forum
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18 years ago

Sytem Verilog one-hot selection

Aren't the new System Verilog case specifiers (unique/priority) supposed to avoid the need of using the synthesis attribute "full_case" ? No matter what I do, I cannot get a one-hot optimized s...
Altera_Forum's avatar
Altera_Forum
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18 years ago

Hi HDL Guru,

I know the online help (and the full manual as well) claims they are supported. I mentioned this already at one of my first posts. But how do you know MySupport is wrong, and not the manual and online help are the ones that are wrong?

I made a couple of tests and it seems indeed the manual is wrong. Not even the parallel semantics seems to be supported (I initially thought the problem was only the full semantics). All you get is some additional warnings at compile time (but not at simulation run-time).

Thanks for testing under ModelSim 6.3. So I was wrong about that. I still think it's not the right simulation behavior. The simulator knows there are no latches, so I don't understand why it preservers the previous value.