Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Sytem Verilog one-hot selection

Aren't the new System Verilog case specifiers (unique/priority) supposed to avoid the need of using the synthesis attribute "full_case" ? No matter what I do, I cannot get a one-hot optimized s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

I received a reply from "MySupport" claiming that "unique" is not supported and it is ignored. This can't be 100% true because you get additional warnings when using the keyword with overlapping case items, and the warnings do reference the System Verilog "unique" feature.

I guess the conclusion is that it is supported by the earlier analysis, parsing phases, but it is ignored at actual shyntesis.

I also checked the ModelSim 6.3 release notes and both "unique" and "priority" are now supported. I hope Altera will update their ModelSim version with newer QII releases (and of course, add full support for the keywords in Quartus as well).