Sytem Verilog one-hot selection

I guess I trust the documentation that ships with the tool rather than a support hotline. :)

Hey, you're right! I played around with some nasty non-parallel case statements. Quartus II 7.2 doesn't force parallel implementation. It just gives you a warning about having overlap in a unique case statement. From the looks of things, Quartus II is implementing unique/priority more as an assert about a design property than a direction to implement the logic in a particular way. That's not terribly useful.

I think I'm coming around to your way of seeing things. Personally, I would have preferred that SystemVerilog introduced an equivalent full keyword rather than making unique/priority absorb the semantics. Then I started thinking, these keywords are really just intended to give designers the same semantics as parallel_case, full_case but with some modicum of simulation support. A warning in simulation is better than nothing, as you said.