Forum Discussion
SystemVerilog static variables
I have a problem with local variables in SystemVerilog/Quartus.
static seems not to be working as expected. The following code generates no output(led constant).
always @(posedge clk) begin : P_1us static logic [5:0] nClk = 6'd0; led <= 1'b0; if( nClk == 50 ) begin led <= 1'b1; nClk = 0; end nClk++; end
8 Replies
- sstrell
Super Contributor
What version/edition of Quartus are you using?
- sstrell
Super Contributor
Lite has limited SystemVerilog support. Maybe that's what you're running into. Are there any warnings when you compile?
- PElm
New Contributor
Does any Altera/Intel staff read this?
Or how do I report errors in Quartus?
- RichardT_altera
Super Contributor
Hi @PElm
You may find the warning messages/ error in the Message GUI at the bottom of the Quartus.
As mentioned here: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/po/ss-quartus-comparison.pdf
Quartus lite/standard has limited supported in System Verilog. I would recommend to run in Quartus Pro or to change to Verilog language.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. - RichardT_altera
Super Contributor
I have yet to receive any response from you to the previous question/reply/answer that I have provided but I believed that I have answered your question.
With that, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.