PElm
New Contributor
4 years agoSystemVerilog static variables
I have a problem with local variables in SystemVerilog/Quartus.
static seems not to be working as expected. The following code generates no output(led constant).
always @(posedge clk) begin : P_1us static logic [5:0] nClk = 6'd0; led <= 1'b0; if( nClk == 50 ) begin led <= 1'b1; nClk = 0; end nClk++; end
However removing "static" it works.
With competing tools(Vivado and more) this work as expected.
It seems static is treated as automatic.