Forum Discussion
PElm
New Contributor
New ContributorSystemVerilog static variables
I have a problem with local variables in SystemVerilog/Quartus.
static seems not to be working as expected. The following code generates no output(led constant).
always @(posedge clk) begin : P...
RichardT_altera
Super Contributor
Super ContributorHi @PElm
You may find the warning messages/ error in the Message GUI at the bottom of the Quartus.
As mentioned here: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/po/ss-quartus-comparison.pdf
Quartus lite/standard has limited supported in System Verilog. I would recommend to run in Quartus Pro or to change to Verilog language.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.
