Forum Discussion
PElm
New Contributor
New ContributorSystemVerilog static variables
I have a problem with local variables in SystemVerilog/Quartus.
static seems not to be working as expected. The following code generates no output(led constant).
always @(posedge clk) begin : P...
sstrell
Super Contributor
Super ContributorLite has limited SystemVerilog support. Maybe that's what you're running into. Are there any warnings when you compile?
