Altera_Forum
Honored Contributor
Honored Contributorsum of element in the array
how could i write this code without clk signal,any suggest is very helpful, thanks
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Altera_Forumif you say sum( = summary )of an array.
how do you specify its timing without clk. why you don't like to use clk? using clk is almost necessary for FPGA development.- Altera_Forum
actually i just want y=p(0)+p(1)+.....p(n-1) (p(i) is element of the array) without clk signal, because in my example i have,y=p(0)+p(1) without clk singal,i try and it work, now i extend for n-1 element, that's all
- Altera_Forum
It's no problem of VHDL syntax, you can write a for loop with a variable for the sum.
If you are asking about hardware synthesis, you are creating a number of cascaded adders so the propagation delay becomes respectively slow. - Altera_Forum
so how to prevert the propagation delay ??? i need it quickly enough
- Altera_Forum
You can't prevent propagation delay, you should design aware of it, e.g. by using synchronous pipelined topology.
It's no clear what you want to achieve. At present it's just a general VHDL syntax question, not related to hardware design. - Altera_Forum
well,i have a project about FIR adaptive, and i need to add all products in filter together to produce the output,i simualte in matlab and use hdl coder to convert vhdl code,then implement in hardwave(not right now,maybe next week )
- Altera_Forum
HDL Coder will give you a pipelined output, and you can control how many pipeline stages there are. Usually you want a register after each adder stage.
- Altera_Forum--- Quote Start --- HDL Coder will give you a pipelined output, and you can control how many pipeline stages there are. Usually you want a register after each adder stage. --- Quote End --- i'm writing in quartus II,my code based on "DSP with FPGA" and the author using lpm_mult ,i don't know how it work???,he just use library lpm
- Altera_Forum
I have across some notes in this book (by Meyaers if I remember correctly). It seems written by software professor who doesn't know much about fpgas
- Altera_Forum--- Quote Start --- I have across some notes in this book (by Meyaers if I remember correctly). It seems written by software professor who doesn't know much about fpgas --- Quote End --- I don't agree. The book isn't particularly focussed on FPGA design methodology, but the FIR examples in meyer-baese digital signal processing with field programmable gate arrays are mostly pipelined. --- Quote Start --- i'm writing in quartus II,my code based on "DSP with FPGA" and the author using lpm_mult ,i don't know how it work???,he just use library lpm . --- Quote End --- Which FIR topology and example design are you referring to?
