Altera_Forum
Honored Contributor
Honored Contributorsum of element in the array
how could i write this code without clk signal,any suggest is very helpful, thanks
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Altera_ForumHonored Contributor
Honored ContributorIt's no problem of VHDL syntax, you can write a for loop with a variable for the sum.
If you are asking about hardware synthesis, you are creating a number of cascaded adders so the propagation delay becomes respectively slow.
