Altera_Forum
Honored Contributor
Honored Contributorsum of element in the array
how could i write this code without clk signal,any suggest is very helpful, thanks
Forum Discussion
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I have across some notes in this book (by Meyaers if I remember correctly). It seems written by software professor who doesn't know much about fpgas --- Quote End --- I don't agree. The book isn't particularly focussed on FPGA design methodology, but the FIR examples in meyer-baese digital signal processing with field programmable gate arrays are mostly pipelined. --- Quote Start --- i'm writing in quartus II,my code based on "DSP with FPGA" and the author using lpm_mult ,i don't know how it work???,he just use library lpm . --- Quote End --- Which FIR topology and example design are you referring to?
