Altera_Forum
Honored Contributor
Honored Contributorsum of element in the array
how could i write this code without clk signal,any suggest is very helpful, thanks
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Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- HDL Coder will give you a pipelined output, and you can control how many pipeline stages there are. Usually you want a register after each adder stage. --- Quote End --- i'm writing in quartus II,my code based on "DSP with FPGA" and the author using lpm_mult ,i don't know how it work???,he just use library lpm
