sum of element in the array

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I have across some notes in this book (by Meyaers if I remember correctly). It seems written by software professor who doesn't know much about fpgas

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do you remember the name of book,he writes about multi_pipeline ???

I wouldn't worry about book names.

If a book says add all terms as y = p0+p1+p2+...+pn

then this is direct algebra that is not helpful for fpga design especially if number of taps is too large because it implies many adders in parallel without any reference to a sampling clock edge.

It also assumes all input stages are available at same time in parallel while in many cases the input is a stream of incoming samples..

In FPGAs and depending on fmax you will need to add in stages(cascade or ladder) with each stage registered before going to next. There is no need to worry about

latency of few samples as filters have intrinsic delay anyway(group delay)

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I don't agree. The book isn't particularly focussed on FPGA design methodology, but the FIR examples in meyer-baese digital signal processing with field programmable gate arrays are mostly pipelined.

Which FIR topology and example design are you referring to?

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about adaptive FIR,he just used filter with order=2,i want more order so that y(n)=p(0)+p(1)+....p(n)

if i write :

sum1<=sum0+produce;

sum2<=sum1+produce;

output<=sum2;

is this pipeline adder ???

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if i write :

sum1<=sum0+produce;

sum2<=sum1+produce;

output<=sum2;

is this pipeline adder ???

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If it is inside a clocked process, yes.

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If it is inside a clocked process, yes.

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when i use hdl coder to convert vhdl without pipeline,so is it very slow if sum1 throught sum 50 ????

anyway, i want to know x and 1/x in vhdl