Altera_Forum
Honored Contributor
Honored Contributorsum of element in the array
how could i write this code without clk signal,any suggest is very helpful, thanks
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Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I don't agree. The book isn't particularly focussed on FPGA design methodology, but the FIR examples in meyer-baese digital signal processing with field programmable gate arrays are mostly pipelined. Which FIR topology and example design are you referring to? --- Quote End --- about adaptive FIR,he just used filter with order=2,i want more order so that y(n)=p(0)+p(1)+....p(n)
