sum of element in the array

I wouldn't worry about book names.

If a book says add all terms as y = p0+p1+p2+...+pn

then this is direct algebra that is not helpful for fpga design especially if number of taps is too large because it implies many adders in parallel without any reference to a sampling clock edge.

It also assumes all input stages are available at same time in parallel while in many cases the input is a stream of incoming samples..

In FPGAs and depending on fmax you will need to add in stages(cascade or ladder) with each stage registered before going to next. There is no need to worry about

latency of few samples as filters have intrinsic delay anyway(group delay)