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Honored ContributorState Machine for SPI Master/Slave Interface
http://www.alteraforum.com/forum/attachment.php?attachmentid=10118&stc=1
Dear all, I am trying to write a state machine that checks to see if correct data is being received on the SPI link by lighting an LED. I have written a code but I am not sure if I am writing the state machine correctly, it definitely does not compile. Here is the code that I have written in relation to the test bench, please find the file attached.library IEEE; -- Reference for VHDL source code
use IEEE.STD_LOGIC_1164.all; -- Package defined in the IEEE (Found in library IEEE)
-- Entity declaration
entity spi_statemachine is
generic (n: positive := 16; -- Number of bits
port (-- Master --
di_m: in std_logic_vector(15 downto 0);
wren_m: in std_logic;
-- Slave --
do_s: out std_logic_vector(15 downto 0);
do_valid_s: out std_logic;
-- Clock operation --
rst_i: in std_logic;
clk_i: in std_logic;
-- Output detection --
correct: out std_logic);
end spi_statemachine;
-- Architecture behaviour
architecture detect of spi_statemachine is
type state_type is (createData, writeData, delay, writeEnable,
checkValid, receivedData, checkFinished, correctIndication); -- Enumeration type
signal state: state_type;
begin
P1: process (clk_i, rst_i) -- Clock and reset
variable dataLength: integer := n; -- Length of data
variable count: integer := 1;
begin
if rst_i = '0' then -- Reset operation used initialize all signals to predetermined state
state <= createData;
elsif clk_i'event and clk_i = '1' then -- Signal attribute used to test for a change on a signal
case state is
when createData =>
state <= writeData;
else
state <= createData;
end if;
when writeData =>
di_m <= std_logic_vector(to_unsigned(dataLength,n)); -- Write data
state <= delay;
when delay =>
count := count + 1;
if (count > 1) then
state <= writeEnable;
count := 0;
else
state <= delay;
end if;
when writeEnable =>
wren_m <= '1';
state <= checkValid;
when checkValid =>
wren_m <= '0';
state <= receivedData;
when receivedData =>
if do_s = di_m then
state <= checkFinished;
end if;
when checkFinished =>
correct <= '1';
when others => null;
end case;
end if;
end process;
end detect;
