State Machine for SPI Master/Slave Interface

I have fixed the syntax errors and my state machine is compiling.

library IEEE; -- Reference for VHDL source code    
use IEEE.STD_LOGIC_1164.all; -- Package defined in the IEEE (Found in library IEEE)
use IEEE.numeric_std.all; -- Used to covert integer to std_logic_vector via unsigned type. Unsigned types represent postive 
								  -- values including zero. The compiler interprets each unsigned type as a binary number, with the 
								  -- digit of the left as the MSB (Most Significant Bit).
-- Entity declaration
entity spi_statemachine is -- Entity name.
	-- Generics --
	generic (n: positive := 16); -- Number of bits. Generic is used to specify parameters, for example, the length of data.
	port (-- Inputs --
         do_o: in std_logic_vector(n-1 downto 0); -- Data in.
         do_valid_o: in std_logic; -- Check if data is valid (No data setup glitches on the data transfer), valid during one 
											  -- clk_i rising edge.
         -- Outputs --
         di_i: out std_logic_vector(n-1 downto 0); -- Data out.
         wren_i: out std_logic; -- Write port, valid during one clk_i rising edge.
         -- Start operation --
         start: in std_logic; -- Start state machine.
         -- Clock operation --
         rst_i: in std_logic; 
         clk_i: in std_logic; -- Clock synchronicity with data.
         -- Output indication --
         correct: out std_logic); -- Check if data transmitted is correct.
end spi_statemachine; -- End entity
-- Architecture behaviour
architecture detect of spi_statemachine is -- Identifying the architecture.
type state_type is (createData, writeData, delay, stopwriteEnable,
                    checkValid, compareData, checkFinished); -- Enumeration types.
                          
-- Signals and types
signal state: state_type; -- State of the machine.
type int_array is array (integer range <>) of integer;
begin
	P1: process (clk_i, rst_i, start) -- Sensitivity list. The process wakes up when an event occurs on one of the signals 
												 -- in the sensitivity list.
   -- Variables -- (Variables change immediately therefore 'rst_i' is used to stop this from happening)
   variable error_rate: natural := 0; -- Incrementing error. Natural is a data type is used to represent natural
												  -- (nonnegative) numbers.
   variable data_in: std_logic_vector(n-1 downto 0); -- Data length. Integer is a data type that represents positive and 
																	  -- negative whole numbers.
   variable data_out: std_logic_vector(n-1 downto 0);
	variable random_data: int_array(0 to 15);
	variable count: integer := 0;
	variable i: integer := 0;
   begin
		if rst_i = '1' then -- Reset operation used initialize all signals to predetermined state.
			-- Initial values for all outputs, variables and signals --
			di_i <= (others => '0'); 
         wren_i <= '0';
         correct <= '0';
         error_rate := 0;
         data_in := (others => '0');
         data_out := (others => '0');
			count := 0;
			i := 0;
			random_data(0) := 14492;
			random_data(1) := 9335;
			random_data(2) := 10648;
			random_data(3) := 21153;
			random_data(4) := 14657;
			random_data(5) := 10583;
			random_data(6) := 10651;
			random_data(7) := 18398;
			random_data(8) := 12598;
			random_data(9) := 30086;
			random_data(10) := 6444;
			random_data(11) := 25436;
			random_data(12) := 25025;
			random_data(13) := 27533;
			random_data(14) := 3525;
			random_data(15) := 31968;
			state <= createData;
			elsif clk_i'event and clk_i = '1' then -- Signal attribute used to test for a change on a signal.
				case state is
					-- When state 'createData' and if 'start' equals '1', then state is 'writeData' and 'i' increments count from
					-- 0 to 15. If 'i' increments count above 15 then 'i' equals 0 and otherwise state is 'createData'.
					when createData =>
						if (start = '1') then
							state <= writeData;
								i := i + 1;
							if (i > 15) then
								i := 0;
							end if;
							else
								state <= createData;
							end if;
                    
					-- 'random_data' is converted into 'std_logic_vector' and is then is written in to 'data_out' and 'di_i'.
					-- 'random_data' will be counted (i) up to 15 (n).
               when writeData =>
						data_out := std_logic_vector(to_unsigned(random_data(i), n));
						di_i <= std_logic_vector(to_unsigned(random_data(i), n));
						state <= delay;
					
               when delay =>
						count := count + 1;
						if	(count > 1) then
							state <= stopwriteEnable;
							wren_i <= '1'; -- Starts transmission.
							count := 0;
						else
							state <= delay;
						end if;
					 
               when stopwriteEnable =>
						state <= checkValid;
                    
					-- If 'do_valid_o' equals '1' then 'do_o' gets the value of 'data_in'. 'wren_i' equals '0' as it only as
					-- only equals '1' for one clock cycle.
               when checkValid =>
						if (do_valid_o = '1') then
							data_in := do_o;
							wren_i <= '0';
							state <= compareData;
                  else
							state <= checkValid;
                  end if;
					-- If 'data_in' equals 'data_out' and the error rate is below '0' then there is no error, if the error 
					-- rate is above '0' then there is an error.
               when compareData =>
						if data_in = data_out then
							error_rate := error_rate - 1;
						else
							error_rate := error_rate + 1;
						end if;
							state <= checkFinished;
                        
					-- If the error rate is greater than '0' then correct equals '0', otherwise correct equals '1'.
               when checkFinished =>
						if (error_rate > 0) then
							correct <= '0';
						else
							correct <= '1';
                  end if;
            end case;
        end if;
    end process;
end detect;