State Machine for SPI Master/Slave Interface

I am still trying to write a state machine that checks to see if correct data is being received between the input 'di_i' and the output 'do_o' but I get the following error message:

Error (10409): VHDL Type Conversion error at spi_statemachine.vhd(89): converted type of object near text or symbol "std_logic_vector" must match integer type of target object

library IEEE; -- Reference for VHDL source code	
use IEEE.STD_LOGIC_1164.all; -- Package defined in the IEEE (Found in library IEEE)
use IEEE.numeric_std.all; -- Used to covert integer to std_logic_vector via unsigned type. 
-- Unsigned types represent postive values including zero. The compiler interprets each
-- unsigned type as a binary number, with the digit of the left as the MSB (Most Significant Bit)
-- Entity declaration
entity spi_statemachine is -- Entity name
	-- Generics --
   generic (n: positive := 16); -- Number of bits. Generic is used to specify parameters, for example, the
										  -- length of data.
	port (-- Inputs --
			di_i: in std_logic_vector(n-1 downto 0); -- Data in
			do_valid_o: in std_logic;	-- Check if data is valid (No data setup glitches on the data transfer),
												-- valid during one clk_i rising edge
			-- Outputs --
			do_o: out std_logic_vector(n-1 downto 0); -- Data out
			wren_i: out std_logic; -- Write port, valid during one clk_i rising edge
			-- Start operation --
			start: in std_logic;	-- Start state machine
			-- Clock operation --
			rst_i: in std_logic; 
			clk_i: in std_logic; -- Clock synchronicity with data
			-- Output indication --
			correct: out std_logic); -- Check if data transmitted is correct
end spi_statemachine; -- End entity
-- Architecture behaviour
architecture detect of spi_statemachine is -- Identifying the architecture
type state_type is (createData, writeData, delay, writeEnable,
						  checkValid, compareData, checkFinished, correctData); -- Enumeration types
						  
-- Signals
signal state: state_type; -- State of the machine
begin
	P1: process (clk_i, rst_i, start) -- Sensitivity list. The process wakes up when an event occurs
												 -- on one of the signals in the sensitivity list.
	-- Variables --
	-- Variables change immediately therefore 'rst_i' is used to stop this from happening.
	variable data: integer := 15; -- Data length. Integer is a data type that represents positive and negative 
											-- whole numbers.
	variable error_rate: natural := 0; -- Incrementing error. Natural is a data type is used to represent natural 
												 -- (nonnegative) numbers.
	variable data_in: integer := 15;
	variable data_out: integer := 15;
	begin
		if rst_i = '1' then -- Reset operation used initialize all signals to predetermined state
			do_o <= (others => '0'); 
			wren_i <= '0';
			correct <= '0';
			data := 15;
			error_rate := 0;
			state <= createData;
			data_in := 15;
			data_out := 15;
		elsif clk_i'event and clk_i = '1' then	-- Signal attribute used to test for a change on a signal
			case state is
				when createData =>
					if (start = '1') then -- Start state machine
						state <= writeData;
					else
						state <= createData;
					end if;
					
				when writeData =>
                                        data_out := std_logic_vector(to_unsigned(data, n)); -- Write data
					state <= delay;
					
				when delay =>
					state <= writeEnable;
				
				when writeEnable =>
					wren_i <= '1';
					state <= checkValid;
					
				when checkValid =>
					if (do_valid_o = '1') then
						data_in := di_i;
						wren_i <= '0';
						state <= compareData;
					else
						state <= writeEnable;
					end if;
				when compareData =>
					if data_in = data_out then
						error_rate := error_rate-1;
					else
						error_rate := error_rate+1;
						state <= checkFinished;
					end if;
						
				when checkFinished =>
					if (error_rate > 0) then
						correct <= '0';
					else
						correct <= '1';
					end if;
			end case;
		end if;
	end process;
end detect;