State Machine for SPI Master/Slave Interface

I am trying to write a test bench for my state machine but I don't seem to be getting the correct results.

The test bench for my state machine is the following code:

library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- Entity --
entity spi_statemachine_test is
   generic (n: positive := 16);
end spi_statemachine_test;
-- Component declaration --
architecture behaviour of spi_statemachine_test is
component spi_statemachine
	port (do_o: in std_logic_vector(n-1 downto 0);
         do_valid_o: in std_logic;
         di_i: out std_logic_vector(n-1 downto 0);
         wren_i: out std_logic;
         start: in std_logic;
         rst_i: in std_logic; 
         clk_i: in std_logic;
         correct: out std_logic);
end component;
		
-- Signals --
signal clk_i: std_logic;
signal start: std_logic;
signal rst_i: std_logic;
signal wren_i: std_logic;						        					                      
signal di_i: std_logic_vector(n-1 downto 0);		
signal do_valid_o: std_logic;                     										 
signal do_o: std_logic_vector(n-1 downto 0);
signal correct: std_logic;
-- Clock period --
constant clk_period: time := 10 ns;
  	
-- Compomemt instantiation --
begin
	C: spi_statemachine
		port map(di_i => di_i,
					wren_i => wren_i,
					do_o => do_o,
					do_valid_o => do_valid_o,
					start => start,
					rst_i => rst_i,
					clk_i => clk_i,
					correct => correct);
				
-- Clock --
clk_process_slave: process
	begin
		clk_i <= '0';
		wait for clk_period/2;
      clk_i <= '1'; 
      wait for clk_period/2;
	end process clk_process_slave;
	
-- Stimulus -- 
stimulus: process is
	variable data_v: std_logic_vector(n-1 downto 0);
		begin
			start <= '1';
			rst_i <= '1';
			do_valid_o <= '0';
			do_o <= (others => '0');
			wait for 15ns;
			rst_i <= '0';
			wait until wren_i'event and wren_i = '1';
			data_v := di_i;
			wait until clk_i'event and clk_i = '1';
			do_o <= data_v;
			wait until clk_i'event and clk_i = '1';
			wait until clk_i'event and clk_i = '1';
			do_valid_o <= '1';
			wait until clk_i'event and clk_i = '1';
			do_valid_o <= '0';
			wait until clk_i'event and clk_i = '1';
			assert correct <= '0'
			report "There in an incorrect value on the output LED)"
			severity error;
			wait for 5ns;
			wait;
end process stimulus;
end behaviour;

The following screenshot is of my simulation, 'correct' should be high because the correct data is being received between 'di_i' and 'do_o'.

https://www.alteraforum.com/forum/attachment.php?attachmentid=10201

Kind regards,

Deadman