Forum Discussion
Altera_Forum
Honored Contributor
11 years ago --- Quote Start --- 1. you forgot to use the numeric_std library in your code (you're converting from integer to slv via an unsigned type). So put at the top use ieee.numeric_std.all; 2. di_m abd wren_m are inputs , you cannot assign a value to input. (line 41, 54, 58). You can only assign values to outputs. 3. The count variable is useless. The first time you're in the delay state it's value will be 2, and you'll go strait to write_enable (learn how signals work vs variables0 4. You cannot read values from outputs (assuming you're trying to compile with VHDL 1993 code). I highly suggest you read the errors. They are usually very descriptive. --- Quote End --- Thank you for your reply. I have read the errors and corrected them, the code is compiling. Do you know how to generate random numbers to inputs and outputs instead if fixed values? Kind regards, Deadman