overD
New Contributor
4 years agoSPI slave to Avalon master bridge core
Hello!
I'm trying to simulate SPI slave to Avalon master bridge core. I can see that when I issue a read transaction then under some conditions the start symbol 0x7c in the core response is lost. It is acknowledged by the MISOctl module but it doesn't appear in the output shift register rdshiftreg. It looks like a sync problem between sclk and system clock domains. Is it something wrong with my setup or is it really a bug in the IP?