Forum Discussion
overD
New Contributor
5 years agoSPI slave to Avalon master bridge core
Hello! I'm trying to simulate SPI slave to Avalon master bridge core. I can see that when I issue a read transaction then under some conditions the start symbol 0x7c in the core response is lost. It...
Nurina
Regular Contributor
5 years agoHi,
Sorry for getting back to you rather late. Can you let me know which module are you simulating in modelsim? Which library can I find this module in?
Can you also let me know which version of Quartus are you using?
Thanks,
Nurina