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overD
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4 years ago

SPI slave to Avalon master bridge core

Hello! I'm trying to simulate SPI slave to Avalon master bridge core. I can see that when I issue a read transaction then under some conditions the start symbol 0x7c in the core response is lost. It...
overD's avatar
overD
Icon for New Contributor rankNew Contributor
4 years ago

Hi,

I use Quartus Prime Version 20.1.1 Lite Edition with Modelsim Intel FPGA Starter Edition 2020.1.

I use spi_test.do as a simulation script. Top level module is spi_test_tb, which instantiates spi_test module and a Qsys testbench with SPI Slave to Avalon Master Bridge IP as a DUT and BFMs. Spi_test module is to provide stimuli on SPI bus.