overDNew Contributor4 years agoSPI slave to Avalon master bridge core Hello! I'm trying to simulate SPI slave to Avalon master bridge core. I can see that when I issue a read transaction then under some conditions the start symbol 0x7c in the core response is lost. It...Show Morewaveform.PNG390 KB
NurinaRegular Contributor4 years agoHi,Can you share you qar file so I can reproduce your problem? Go to Project->Archive ProjectThanks,Nurina
overDNew Contributor to Nurina4 years agoHi, Nurina! Here is my Quartus project with a testbench.spi_test_sys.qar105 KB
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