Source Synchronous Center Aligned Input - deriving constraint

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I am targeting TI's TUSB1310A device and it has center-aligned output timing as shown in attached. Does this translate to an ideal set_input_delay -max = 0 ns and -min = -1 ns?

Regards,

Mark

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No, if fpga receive data on pclk then min is 1 and max is 2 assuming clk and data has same board delay.

definition of input delay is the offset from clock edge.

Are my constraints below correct?

create_clock -period 4.0 -name pclk [get_ports pclk]

derive_pll_clocks

derive_clock_uncertainty

# Create virtual clock for TIUSB1310A

create_clock -period 4.0 -name pclk_ext

set_input_delay -clock pclk_ext -max 2 [get_ports {rx_data[*]}]

set_input_delay -clock pclk_ext -min 1 [get_ports {rx_data[*]}]

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Are my constraints below correct?

create_clock -period 4.0 -name pclk [get_ports pclk]

derive_pll_clocks

derive_clock_uncertainty

# Create virtual clock for TIUSB1310A

create_clock -period 4.0 -name pclk_ext

set_input_delay -clock pclk_ext -max 2 [get_ports {rx_data

[*]}]

set_input_delay -clock pclk_ext -min 1 [get_ports {rx_data

[*]}]

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That looks ok to me.

Other signals apart from data as per your diagram also require same delay figures.

clock uncertainty can be entered from your chip data sheet if available

Yes, I need to add all the relevant input signals.

I'm still unsure of the virtual clock. Do I need to specify that there is a shift as shown below? Or does the input delay constraint take care of it already?

create_clock -period 4.0 -name pclk_ext [get_ports pclk] -waveform {2.0 4.0}

Thanks for the feedback!

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Yes, I need to add all the relevant input signals.

I'm still unsure of the virtual clock. Do I need to specify that there is a shift as shown below? Or does the input delay constraint take care of it already?

create_clock -period 4.0 -name pclk_ext [get_ports pclk] -waveform {2.0 4.0}

Thanks for the feedback!

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You only need to shift virtual clock if offset figures (1,2 ns) are relative to another clock outside fpga and not to pclk that is received at fpga pins as data clock.

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Not including board skew, based on the timing spec from TI, I shouldn't need to phase shift the FPGA clock unless timing is not met. Is this right?

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If there is board delay difference between pclk and data then you need to adjust TI spec figures then apply the modified min/max delay.

If it passes timing then you don't need PLL in the first place. If it doesn't then the popular solution is rotate the clock in a pll.

If you do use PLL, the source synchronous mode is meant to maintain data/clock relationship at pins right through to the registers. In other words it is meant for the case when PLL is not designed to rotate the clock.