Source Synchronous Center Aligned Input - deriving constraint

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Are my constraints below correct?

create_clock -period 4.0 -name pclk [get_ports pclk]

derive_pll_clocks

derive_clock_uncertainty

# Create virtual clock for TIUSB1310A

create_clock -period 4.0 -name pclk_ext

set_input_delay -clock pclk_ext -max 2 [get_ports {rx_data

[*]}]

set_input_delay -clock pclk_ext -min 1 [get_ports {rx_data

[*]}]

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That looks ok to me.

Other signals apart from data as per your diagram also require same delay figures.

clock uncertainty can be entered from your chip data sheet if available