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Altera_Forum
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12 years ago

Source Synchronous Center Aligned Input - deriving constraint

I am targeting TI's TUSB1310A device and it has center-aligned output timing as shown in attached. Does this translate to an ideal set_input_delay -max = 0 ns and -min = -1 ns? Regards, Ma...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Not including board skew, based on the timing spec from TI, I shouldn't need to phase shift the FPGA clock unless timing is not met. Is this right?