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Altera_Forum
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12 years ago

Source Synchronous Center Aligned Input - deriving constraint

I am targeting TI's TUSB1310A device and it has center-aligned output timing as shown in attached. Does this translate to an ideal set_input_delay -max = 0 ns and -min = -1 ns? Regards, Ma...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Are my constraints below correct?

create_clock -period 4.0 -name pclk [get_ports pclk]

derive_pll_clocks

derive_clock_uncertainty

# Create virtual clock for TIUSB1310A

create_clock -period 4.0 -name pclk_ext

set_input_delay -clock pclk_ext -max 2 [get_ports {rx_data[*]}]

set_input_delay -clock pclk_ext -min 1 [get_ports {rx_data[*]}]