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Altera_Forum
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12 years ago

Source Synchronous Center Aligned Input - deriving constraint

I am targeting TI's TUSB1310A device and it has center-aligned output timing as shown in attached. Does this translate to an ideal set_input_delay -max = 0 ns and -min = -1 ns? Regards, Ma...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Yes, I need to add all the relevant input signals.

I'm still unsure of the virtual clock. Do I need to specify that there is a shift as shown below? Or does the input delay constraint take care of it already?

create_clock -period 4.0 -name pclk_ext [get_ports pclk] -waveform {2.0 4.0}

Thanks for the feedback!