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Altera_Forum
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12 years ago

Source Synchronous Center Aligned Input - deriving constraint

I am targeting TI's TUSB1310A device and it has center-aligned output timing as shown in attached. Does this translate to an ideal set_input_delay -max = 0 ns and -min = -1 ns? Regards, Ma...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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I am targeting TI's TUSB1310A device and it has center-aligned output timing as shown in attached. Does this translate to an ideal set_input_delay -max = 0 ns and -min = -1 ns?

Regards,

Mark

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No, if fpga receive data on pclk then min is 1 and max is 2 assuming clk and data has same board delay.

definition of input delay is the offset from clock edge.