Source Synchronous Center Aligned Input - deriving constraint

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Yes, I need to add all the relevant input signals.

I'm still unsure of the virtual clock. Do I need to specify that there is a shift as shown below? Or does the input delay constraint take care of it already?

create_clock -period 4.0 -name pclk_ext [get_ports pclk] -waveform {2.0 4.0}

Thanks for the feedback!

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You only need to shift virtual clock if offset figures (1,2 ns) are relative to another clock outside fpga and not to pclk that is received at fpga pins as data clock.