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Not including board skew, based on the timing spec from TI, I shouldn't need to phase shift the FPGA clock unless timing is not met. Is this right?
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If there is board delay difference between pclk and data then you need to adjust TI spec figures then apply the modified min/max delay.
If it passes timing then you don't need PLL in the first place. If it doesn't then the popular solution is rotate the clock in a pll.
If you do use PLL, the source synchronous mode is meant to maintain data/clock relationship at pins right through to the registers. In other words it is meant for the case when PLL is not designed to rotate the clock.
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