Some commands that worked at ModelSim do not work at QuartusII

Question

Hi,

In order to explore the features of ModelSim, I successfully compiled some examples present in the tutorial folder.

However, I willed to synthesize one of these projects at QuartusII, but failed at the following line:

@(posedge clk) while (rdy != 0) @(posedge clk) ;

...returning this error:

--- Quote Start ---

loop with non-constant loop condition must terminate within 250 iterations

--- Quote End ---

Although I noticed at the Web the same message above on various posts, I could not find any one whose reason is similar to that command sequence. Could someone give a tip ?

Thanks in advance.

altera_forum · Answer

while and for loops create one instance of hardware for every iteration. The number of iterations must be known at compile time. you want to code this as always @(posedge clk) if (rdy == 0) ...

altera_forum · Answer

But the piece of the code above is at the middle of an always block. Is there some alternative to replace that ?   I´m assuming that I can´t insert an always block inside another.

altera_forum · Answer

Remember that verilog and vhdl aren't software, they generate hardware. To do something at the first clock edge when rdy is 1 use: 
always @(posedge(clk))
begin
   if (rdy == 1)
      stuff to do goes here
   endif
end
 This will synthesize into what I think you are after.

altera_forum · Answer

hi Galfonz,   I replaced the original line bellow, not buildable by compiler ... @(posedge clk) while (rdy != 0) @(posedge clk) ; ...for the following, that supposedly would synthesize something with a same behavior: always @(posedge(clk))                         // error pointed to this line
	begin
	   if (rdy == 1)
		  @(posedge clk)
	   endif                               // also tried end
	end but now I got the following error:   --- Quote Start ---  Verilog HDL syntax error at proc.v(55) near text "always";  expecting "end"  --- Quote End ---    There are another way to replace the original @(...)while...@(...) sequence for another one more compatible with various compilers ?

altera_forum · Answer

The difference between both tools is (in simplified view):

Modelsim is simply interpreting HDL code line-by-line, it has no limitations to act on multiple clock inputs or perform endless iteration loops, except those set by computer memory and execution time.

A synthesis tool needs to map Verilog or VHDL syntax to hardware, combinatorial logic and flipflops. You must be aware of the fact that only part of the language constructs that can be written in Verilog or VHDL is actually accepted for hardware synthesis.

The nested @(posedge clk) construct can't be mapped to hardware, with or without the if condition.

--- Quote Start ---

There are another way to replace the original @(...)while...@(...) sequence for another one more compatible with various compilers ?

--- Quote End ---

Probably. But we need an example with an actually executed statement, e.g. a variable assignment to suggest an equivalent construct. Preferably a "full design" with inputs and outputs.

Instead of explaining in detail why the examples aren't synthesizable, I suggest to use the Verilog language templates offered in the context menu of the Quartus editor as a starting point. A clocked design that waits for some input signals can be best coded as a finite state machine, at least the non-trivial cases.

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Some commands that worked at ModelSim do not work at QuartusII

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