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Altera_Forum's avatar
Altera_Forum
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11 years ago

Some commands that worked at ModelSim do not work at QuartusII

Hi, In order to explore the features of ModelSim, I successfully compiled some examples present in the tutorial folder. However, I willed to synthesize one of these projects at QuartusII,...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Remember that verilog and vhdl aren't software, they generate hardware. To do something at the first clock edge when rdy is 1 use: 


always @(posedge(clk))
begin
   if (rdy == 1)
      stuff to do goes here
   endif
end

This will synthesize into what I think you are after.