Some commands that worked at ModelSim do not work at QuartusII

The difference between both tools is (in simplified view):

Modelsim is simply interpreting HDL code line-by-line, it has no limitations to act on multiple clock inputs or perform endless iteration loops, except those set by computer memory and execution time.

A synthesis tool needs to map Verilog or VHDL syntax to hardware, combinatorial logic and flipflops. You must be aware of the fact that only part of the language constructs that can be written in Verilog or VHDL is actually accepted for hardware synthesis.

The nested @(posedge clk) construct can't be mapped to hardware, with or without the if condition.

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There are another way to replace the original @(...)while...@(...) sequence for another one more compatible with various compilers ?

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Probably. But we need an example with an actually executed statement, e.g. a variable assignment to suggest an equivalent construct. Preferably a "full design" with inputs and outputs.

Instead of explaining in detail why the examples aren't synthesizable, I suggest to use the Verilog language templates offered in the context menu of the Quartus editor as a starting point. A clocked design that waits for some input signals can be best coded as a finite state machine, at least the non-trivial cases.