Forum Discussion
Altera_Forum
Honored Contributor
11 years agoHello,
Thank you both very much for the pretty enlightening explanation. I did not realize up to now that the Modelsim "variant" of Verilog compiler do not aim to necessarily give support for synthesis, but simulation, what in fact makes all sense, once it can deal with a wide range of nested commands, as the one above. What indeed happened is that I took a sample example verilog project available at the tutorial folder of Modelsim, composed of a code and obviously its associated testbench, and my expectation was to find not so much errors as noticed. What I suppose to be the correct procedure is to create a project in the tool of the manufacturer (Altera, in this case), and afterward use the Modelsim just as an 'advanced tool' due at this sequence the chance to face to some inconsistency at language will be reduced, it´s right ?