Some commands that worked at ModelSim do not work at QuartusII

hi Galfonz,

I replaced the original line bellow, not buildable by compiler ...

@(posedge clk) while (rdy != 0) @(posedge clk) ;

...for the following, that supposedly would synthesize something with a same behavior:

always @(posedge(clk))                         // error pointed to this line
	begin
	   if (rdy == 1)
		  @(posedge clk)
	   endif                               // also tried end
	end

but now I got the following error:

--- Quote Start ---

Verilog HDL syntax error at proc.v(55) near text "always"; expecting "end"

--- Quote End ---

There are another way to replace the original @(...)while...@(...) sequence for another one more compatible with various compilers ?