Simulation Results Always Show Don't Care?

I suggest don't use buffer ports. Instead use an internal signal in order to have internal access

It basically don't work to have part of the clock divider logic outside the clock edge sensitive condition. This way, no Flipflop for clkOut can be inferred.

'X' in std_logic doesn't mean don't care - it means "Forcing Unknown" - i.e. the simulator is trying to drive a '1' or '0' onto the signal but it can't determine which. This can be for several reasons such as putting 'U' into an arithmetic function; but very commonly it can be because you have two drivers for one signal - e.g. two processes which both try and drive the same signal. In logic terms this is like wiring up the outputs of two gates or registers together - the wire will be driven to some value as one or other of the gates is likely to be stronger than the other, but whether the high driving gate is stronger than the low driving one is unpredictable: so in simulation you end up with 'X'.

process(clk)
begin
-- don't put anything here
    if clk'event and clk = '1' then
        -- put your code here
    end if;
-- don't put anything here
end process;

First off thank you to parrado, FvM and batfink for your time and advice. Indeed I have a lot to learn even simple designs can trip you over! Anway, attached are 3 images from the RTL viewer (basically the synthesis results). The first image is that of my original faulty design. The second image is one for the following changed working code. Basically, all I changed was to bring all code into the clk'EVENT conditional (clkOut still declared as BUFFER). Finally, the last image is one that includes the above change plus declaring clkOut as OUT, ie using an internal signal to drive clkOut---those aspects of the code appear as comments in the snippet below. Both the final designs simulate well and notice that removing BUFFER added an additional output flip-flop but everything else is the same.

-- Frequency Divider (must be multiple of 2)
-- Author : Hitesh Patel, October 2008
--          blog.nirosoftware.com
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY FrequencyDivider IS
    GENERIC (NumBits : INTEGER := 26);
    PORT( clkIn : IN STD_LOGIC;
          divisor : IN STD_LOGIC_VECTOR(NumBits-1 DOWNTO 0); -- 26 bits, must be multiple of 2
          clkOut : BUFFER STD_LOGIC);
END FrequencyDivider;
ARCHITECTURE FrequencyDivider OF FrequencyDivider IS
BEGIN
    PROCESS(clkIn)
        VARIABLE count : STD_LOGIC_VECTOR(NumBits-2 DOWNTO 0);
        --VARIABLE clkOut_t : STD_LOGIC;
    BEGIN
        IF(clkIn'EVENT AND (clkIn = '1')) THEN
            count := count + 1;
            IF(count = divisor(NumBits-2 DOWNTO 1)) THEN
                --clkOut_t := NOT clkOut_t;
                --clkOut <= clkOut_t;
                clkOut <= NOT clkOut;
                count := (OTHERS => '0'); 
            END IF;
        END IF;
    END PROCESS;
END FrequencyDivider;

You results are as I would expect them. The additional flip-flop is generated, when you assign the internal signal to the output under the clock sensitive condition. Usually the assignment of outputs would be done in concurrent code (outside the process) without inferring an additional flip-flop.