Simulation Results Always Show Don't Care?

First off thank you to parrado, FvM and batfink for your time and advice. Indeed I have a lot to learn even simple designs can trip you over! Anway, attached are 3 images from the RTL viewer (basically the synthesis results). The first image is that of my original faulty design. The second image is one for the following changed working code. Basically, all I changed was to bring all code into the clk'EVENT conditional (clkOut still declared as BUFFER). Finally, the last image is one that includes the above change plus declaring clkOut as OUT, ie using an internal signal to drive clkOut---those aspects of the code appear as comments in the snippet below. Both the final designs simulate well and notice that removing BUFFER added an additional output flip-flop but everything else is the same.

-- Frequency Divider (must be multiple of 2)
-- Author : Hitesh Patel, October 2008
--          blog.nirosoftware.com
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY FrequencyDivider IS
    GENERIC (NumBits : INTEGER := 26);
    PORT( clkIn : IN STD_LOGIC;
          divisor : IN STD_LOGIC_VECTOR(NumBits-1 DOWNTO 0); -- 26 bits, must be multiple of 2
          clkOut : BUFFER STD_LOGIC);
END FrequencyDivider;
ARCHITECTURE FrequencyDivider OF FrequencyDivider IS
BEGIN
    PROCESS(clkIn)
        VARIABLE count : STD_LOGIC_VECTOR(NumBits-2 DOWNTO 0);
        --VARIABLE clkOut_t : STD_LOGIC;
    BEGIN
        IF(clkIn'EVENT AND (clkIn = '1')) THEN
            count := count + 1;
            IF(count = divisor(NumBits-2 DOWNTO 1)) THEN
                --clkOut_t := NOT clkOut_t;
                --clkOut <= clkOut_t;
                clkOut <= NOT clkOut;
                count := (OTHERS => '0'); 
            END IF;
        END IF;
    END PROCESS;
END FrequencyDivider;