Simulation Results Always Show Don't Care?

It basically don't work to have part of the clock divider logic outside the clock edge sensitive condition. This way, no Flipflop for clkOut can be inferred.

There may be also a problem in comparing signals of different bitwidth.

A power of two divider ratio can be simply achieved by allowing an overflow of the counter (don't need any compare or reset to 0) and using the MSB as output signal (if a 50% duty cycle is intended).