Simulation Results Always Show Don't Care?

You results are as I would expect them. The additional flip-flop is generated, when you assign the internal signal to the output under the clock sensitive condition. Usually the assignment of outputs would be done in concurrent code (outside the process) without inferring an additional flip-flop.

You also showed, that the doubts, that have been worded regarding the usage of a buffer port are apparently unfounded. That's also according to my experience, although I think, that using an internal signal (and assigning it delayless in concurrent code to the outut port) is a better style.