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Altera_Forum
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17 years ago

Simulation Results Always Show Don't Care?

Hello All, I am very new at digital design and am learning on an Altera DE2-70 using VHDL. I have the following code snippet which always shows "Don't Care (XXX)" for the simulation results (cl...
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Altera_Forum
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17 years ago

I suggest don't use buffer ports. Instead use an internal signal in order to have internal access