Simulating FiFo IP using Quartus Pro 23.3

Hello,

I am attempting to simulate the Fifo IP using the Questa Starter Edition. I am targeting the Stratix 10 GX. It is imperative that I use Quartus Pro and Questa SE to perform these simulations. Here are the steps I am taking,

Steps Im taking: Quartus Prime Pro 23.3, Questa Free Standard

1. New Project Wizard
1. Dir: D:/Work/QuestaSims/SingleClk24to24Fifo
2. Name: Fifo
3. Top: FifoTop
4. Stratix 10 GX
5. No added files
6. Select “Questa Intel FPGA edition” for simulation
2. Open Fifo IP editor
1. Everything Default
2. Generate HDL (VHDL)
1. Selected Model Sim for simulator script
3. Generate TestBench
1. Selected VHDL
4. Close Parameter editor
3. Add tb qsys to project files
4. Click "Generate Simulator Setup scripts" under tools

Its at this point that I am unable to make any more progress. I have followed the Questa tutorials provided by Siemans, in the tutorial documents found within the questa install directory. However, these don't account for the added files generated by the IP. I am wondering what steps I need to take after these, so that I have all the needed files to begin simulation?

I have referenced these documents

• Introduction to Intel® FPGA IP Cores
• Intel® Stratix® 10 Embedded Memory User Guide
• Advanced Platform Designer (Part 1): Simulation