Forum Discussion
Honored ContributorSimplest method to transmit a file to FPGA
Provided that one has a file that is to be transmitted down to the FPGA and it will store every byte into internal or external memory (maximum size is around 1MegaByte). What is the preferred way of doing this?
Should one create a custom solution in whic the user sends the file down serial port from PC, the FPGA recieves it into a FIFO and then it stores it in internal/external memory on a per-byte or per-byte-block basis. Or is it possible to utilize the JTAG port for this purpose such that the file can be streamed down the JTAG port and the design inside the FPGA can process the bytes as stated above? I expected this to be a simple problem since we already transmit configuration data to the FPGA and possibly a connected configuration memory device. However, it seems that it is not. :|13 Replies
Altera_ForumHi,
you can use the JTAG-UART IP Core. It simulates a UART interface via JTAG. Have a look at page 53. https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_embedded_ip.pdf If you use UART for such a huge file, you should implement an error correction functionality. For example use Checksums and request invalid data again. The easiest way should be using a NIOSII. Greets Olaf- Altera_Forum
I take this to mean that no reference design exists for this purpose,
you mean that the error correction can be implemented in software in a nios II? since the issue of checksum has been raised, do you mean that there should be checksum for the whole file or for chunks e.g every 256 bytes? Certainly the checksum shall have to be generated and stored within the file itself too. UART does not have a means to send acknowledge signal but RS232 may have it. Now specifically what do you imagine would be the application used to transmit the file from PC to the FPGA? I assume you envision a custom application. - Altera_Forum
On a second thought, as far as I vaguely understand, there is also a method by which such extra data can be bundled together with the FPGA configuration data and together with this configuration data be burned onto a configuration memory. Perhaps this will be a faster way to get this data onto a flash so the design can read it out and send it to the data converters?
- Altera_Forum
Hi Xaui, I am searching for an answer to this same question. In particular, Altera's Frame Reader VIP IP core accesses an image stored in SDRAM. It's likely that anyone implementing a circuit including that Frame Reader might have wanted to copy a BMP or TIF from the PC's file system into SDRAM. I would expect there to be an out-of-the-box solution by now. Have you found a good answer? Hopeful thanks ...
- Altera_Forum
PCIe would be the obvious choice, but that's complicated and potentially expensive if you're not using a device that has the hard PCIe IP built in. For simple and cheap you can't beat a UART. In this case you can't read the file out of PC memory, you would need an application on the PC transferring the file to you using the UART. But you can use terminal emulators like Teraterm to do this. UARTs are slow, but pretty darn easy to implement and to debug. You can at least star there to get the ball rolling and then upgrade to improve performance as needed.
Bob - Altera_Forum
Thanks, Bob, for this clear advice.
Download speed is not yet an issue; I'm studying 720p/1080p images first. "Use a UART" includes implementing a device driver / ISR for Nios II. I guess I'll follow https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an459.pdf. That teaches how to connect my starter kit's USB port to the FPGA. It remains to: 1) Set up a terminal emulator to send a TIF/BMP file from the development PC's disk drive to the USB blaster / UART emulator 2) Write Nios code to format the received bits as the 4-byte 0/R/G/B words in SDRAM, as expected by the Frame Reader core. Is there anything else to consider? Am I making this too complicated? Implementing a minimal FPGA pipeline to display the downloaded file via the HDMI TX port on the starter kit seems relatively straightforward. It seems to me that pretty much all you guys out there who've used a TerasIC C5G dev kit would have solved this already. Why would we each roll our own? Cheers --todd - Altera_Forum
Hey Todd -
It would not be difficult at all to do this without a NIOS, but do what you're most comfortable with. You'll want to transfer the file in binary mode. If you have the NIOS you might want to write some code to write a test pattern image to memory so you can test the display path before pulling in live images from the PC. Debugging one piece at a time is always easier. And get familiar with SignalTap if you're not yet. It's a great debug tool (in support of simulation). Good luck! Bob - Altera_Forum
Hi Bob,
Thank you for this further advice. I've already got the display path working (as I said, it's relatively easy). I'll press on. People keep telling me how easy it is to do this, without pointing to a complete solution. I shudder to imagine things that *aren't* considered easy in this context :^) Cheers --todd - Altera_Forum
Hi again guys,
Here's a convenient solution. Again, I'm working on an image processing circuit and don't want to spend time now messing around with image file I/O. I'm using a terasIC dev kit with an HDMI TX on it. The kind folks at terasIC showed me a short-cut to achieve the objective of initializing the SDRAM with a test image file: 1. in Quartus programmer, configure the kit with Control_Panel.sof 2. in terasIC Control Panel, click the "copy file to SDRAM" button, which provides GUI browsing to the file on my PC's drive 3. in Quartus programmer, configure the kit with my circuit.sof At reset, my Nios needs to tell the Frame Reader to start reading a 1080p frame from SDRAM location 0. Now I reckon that's a lot easier than implementing my own UART driver! If I'm overlooking something, please let me know. If anyone else ever benefits from reading this solution, please let me know. Cheers --todd - Altera_Forum
To refine the solution: Assume the input image is a BMP file.
The Nios code should first read byte A, which holds the address (usually 6'h36) in the BMP file where the pixel data starts. Initialize the Frame Reader IP core to start from the indicated location, then write GO. Cheers --todd --- Quote Start --- Hi again guys, Here's a convenient solution. Again, I'm working on an image processing circuit and don't want to spend time now messing around with image file I/O. I'm using a terasIC dev kit with an HDMI TX on it. The kind folks at terasIC showed me a short-cut to achieve the objective of initializing the SDRAM with a test image file: 1. in Quartus programmer, configure the kit with Control_Panel.sof 2. in terasIC Control Panel, click the "copy file to SDRAM" button, which provides GUI browsing to the file on my PC's drive 3. in Quartus programmer, configure the kit with my circuit.sof At reset, my Nios needs to tell the Frame Reader to start reading a 1080p frame from SDRAM location 0. Now I reckon that's a lot easier than implementing my own UART driver! If I'm overlooking something, please let me know. If anyone else ever benefits from reading this solution, please let me know. Cheers --todd --- Quote End ---
