Signal Tap II display signals?

In my trigger condition selection, I just have the options basic and advanced. When advanced is selected, It opens up a new window where components can be placed etc. which I don't think is necessary. What are you using for your serial configuration clock on the right hand side of set-up? On mine I am using clock_50 which corresponds to the 50MHz clock on my board. I am not sure if this is correct.

I have even created simple frequency divider VHDL code and I still can't get this to work. I have a counter counting up to 50 and then back to 0. I wish to capture just 0 to 10 of this counter. When I press the trigger, which is a negative edge on the push button, it states that it is acquiring post-trigger data and just does nothing.

Here is my code

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
------------------------------------------------------------------
ENTITY freq_divider IS
PORT ( clock_50 : IN STD_LOGIC;
		 button : IN STD_LOGIC;
		 clk : OUT STD_LOGIC
		);
END freq_divider;
------------------------------------------------------------------
ARCHITECTURE behaviour OF freq_divider IS
SIGNAL count1 : INTEGER:= 0;
SIGNAL count2 : INTEGER:= 0;
SIGNAL counter : INTEGER:= 0;
--SIGNAL bufclk : STD_LOGIC;
SIGNAL freq1 : STD_LOGIC;
SIGNAL freq2 : STD_LOGIC;
SIGNAL freq3 : STD_LOGIC;
SIGNAL freq4 : STD_LOGIC;
BEGIN
--bufclk<= clock_50; 
PROCESS (clock_50)
VARIABLE GO : STD_LOGIC:= '0';
BEGIN
	IF (button = '0') THEN
		GO := '1';
	END IF;
		
	IF (clock_50'EVENT AND clock_50 = '1' ) THEN
		count1 <= count1 + 1;
		IF (count1 >= 200) THEN
			count1<= 0;
			counter<= counter +1;
			IF (counter = 50) THEN
				counter<= 0;
			END IF;
			
			freq1<= NOT(freq1);
		END IF;
	END IF;
END PROCESS;
PROCESS (freq1)
BEGIN
	IF (freq1'EVENT AND freq1 = '1') THEN
		count2 <= count2 + 1;
		IF (count2 >= 50) THEN
			count2<= 0;
			freq2<= NOT(freq2);
			clk<=freq2;
		END IF;
	END IF;
END PROCESS;
END behaviour;
---------------------------------------------------------------------------------------------
		
	

That usually occurs when the trigger events are not happening. Are these signals connected to anything except signaltap, that have an effect on an output? if they're not, you will need syn_keep attributes to prevent the synthesisor removing them.

NOTE: Dividing clocks like this is not recommended if you are driving other logic with them.

Thanks again. Now I changed the clock in the serial configuration on the right hand side to a much lower frequency and I can see the signals changing as they should. I was previously using the 50MHz clock for this.

My counter signal however which is added as a node is not counting in the window as the signals change. It stays at 00H which is incorrrect. This counter is defined as an integer in the VHDL code. Is there any reason that it is not displaying the counting? I was expecting to see it count to 10 as this is the start and stop storage condition. All the other signals are changing as expected however.

Has it been removed like I said? it is possible to add signal names from code only for the synthesisor to remove them. If this is the case you're viewing a signal that no longer exists, but you usually get warning for this.

Having it as an integer is not ideal for signaltap. see if you can find the signal in the "post synthsis" group of registers. As its an integer it will have made the bus 32 bits wide.

It seems that you are learning.* Figuring things out yourself is part of the learning process.* I am not going to point out anything obvious.* There are a few not so obvious ones I can tell you.

1. You need to learn to verify your design in simulator.* That's part of HDL design flow.

2. If you do use SignalTap to verify as a shortcut of avoiding learning to write testbench, you need to start from beginning: verify one counter and register at a time. Don't start from the end without knowing if circuit leading to the final result is correct.* (Often, the tool is working correctly. Think about your error, not the tool.)* You can add all signals to reduce compilation time since your design is small.* In SignalTap, you can leave the storage qualifier feature on, but disable.* Enable/disable it doesn't require you to recompile, a compilation time saver.* You may find that verifying in simulator will be more productive in long run.* Don't take too much shortcut.

3. Don't use that pulse, freq, as the clock, but as a clock enable signal.* In FPGA, it's never a good idea to use gated clock, unless you know compiler can implement it with special hard clock network circuit on the device.* The timing closure with gated clock is hard.* The compiler is getting better at it.* You cannot rely on it still* Designing a fully synchronized design on simple clock is a key to success in FPGA world.* If learning clock divider is not part of objective, you should be using PLL clock divider instead, a hard device feature.

Have fun learning.